Design of an 8-bit Multiplier Using 250 nm CMOS Technology
Specifications
- Code
- MA2616
- Department
- DKM
- Technology
- CMOS 250 nm
- Theme
- Microelectronics
- Student
- Iman Nur Qadisha binti Mohamed Asri
- Supervisor
- Norhafizan bt Mohd Hanib
Objectives
To design and verify the functionality of the 8-bit multiplier circuit using 250nm CMOS technology in Siemens EDA. To optimise the proposed 8-bit multiplier by reducing its average power dissipation compared with a conventional 8-bit multiplier. To evaluate the performance of the proposed multiplier circuit by comparing it with the conventional design based on selected performance metrics.
Scope of project
The project focuses on the transistor-level schematic design, simulation and functional verification of the proposed CMOS circuit using Siemens EDA and 250 nm CMOS technology. The conventional and proposed 8-bit multiplier circuits will be simulated using a 5V supply voltage. Both designs will be tested under the same input patterns, input frequency, temperature, and output load conditions. The performance of the proposed multiplier will be evaluated and compared with the conventional multiplier based on average power dissipation.
Project description
Design an 8-bit CMOS multiplier using 250 nm CMOS technology in Siemens EDA. Perform binary multiplication accurately using the designed circuit. Develop three multiplier designs using different full adders: 28T, 10T, and 8T. Simulate and verify the functionality of each design. Compare the average power dissipation of the three designs. Identify a more power-efficient multiplier design.