Design and Simulation of Low Power 4-bit Priority Encoder in 250 nm CMOS Technology Using Siemens EDA Tools
Specifications
- Code
- MA2620
- Department
- DKM
- Technology
- CMOS 250 nm · Siemens EDA
- Theme
- Microelectronics
- Student
- Zulhilmi Irfan bin Md Ariff @ Fadilah
- Supervisor
- Norhaida bt Mustafa
Objectives
To Design And Implement The Transistor Level CMOS Schematic of a 4-Bit Priority Encoder To develop Low Power Priority Encoder using 250nm CMOS Technology via Siemen EDA To analyze the circuit performance against conventional CMOS design to quantify power saving
Scope of project
Implementation of the Schematic Using PMOS and NMOS Transistors. Design in 250 Nm CMOS Technology Utilizing the Siemens EDA Tools. Validation Is Confined to Functional Logic Testing Via Testbench Waveforms and Manual Verification Using A Truth Table. Analysis Is Strictly Focused On Power Consumption Designing Schematic Design, Performance Simulation and Physical Layout Verification (DRC & LVS).
Project description
A priority encoder converts four input lines into a 2-bit binary code that represents the highest-priority active input. It is widely used in interrupt controllers and arbitration circuits. This project designs the encoder using three transistor-level logic styles to find the most power-efficient one. Boolean equations: Y1 = D3 + D2 | Y0 = D3 + D2′·D1 | V = D3 + D2 + D1 + D0 Method: Truth table → S-Edit schematic → Eldo simulation (waveform and power) → L-Edit layout → DRC and LVS. Result: All three designs matched the truth table and passed DRC and LVS. PTL achieved the lowest power dissipation of [0.28130 nW], which is [33.00]% lower than the Conventional design.